1. Field of the Invention
This disclosure generally relates to structures of a chip-side redistribution layer (RDL) and methods of making a chip-side RDL that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads of varying heights may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that those electrical connectors formed on polyimide pads of a greater height are disposed at a greater radial distance from the center of the IC chip, i.e., on the IC chip's edges and corners, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by warpage, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier in the making of the flip chip package.
2. Description of Related Art
The semiconductor marketplace continues to demand smaller devices, which require greater connectivity densities for packaging design. The increased functionality of smaller semiconductor devices requires an increased number of signal, power, and ground connections, and a corresponding decrease in connection pitch is required to maintain reasonable chip size. The combination of these requirements results in greater complexity of semiconductor packaging design.
The packaging design requirement is especially critical in flip chip packages, where demand for a greater density of connections must coexist with good electrical and thermal reliability performance. When compared to other packaging technologies, a flip chip package, as shown in FIG. 1, significantly increases the number of signal, power and ground connections that connect an integrated circuit (IC) 110 chip to a chip carrier 120 through solder bumps or copper (Cu) pillars 130.
During the chip-join processes of packaging, the solder bumps or Cu pillars 130 form electrical connections to the flip chip (FC) attaches 140 on the chip carrier 120. The solder bumps or Cu pillars 130 are formed on underlying underbumps or ball limiting metallurgy (BLM) structures that are formed on the IC chip 110. Joining of the IC chip 110 to the chip carrier 120 requires heating of the solder bumps or Cu pillars 130, so as to “wet” the opposing solder surfaces of the solder bumps or Cu pillars 130 and the solder of the FC attaches 140. This wetting allows the opposing miscible solders to form an effective electrical connection. An electrical signal, power or ground travels from the FC attach 140 through the chip carrier 120 to a ball grid array land 150 for further packaging structures.
During the first phase of packaging, the flip chip-join of the solder bumps or Cu pillars is adversely affected by warpage, which varies as a function of temperature. At elevated temperatures, both the IC chip and the chip carrier warp because of mismatches between the coefficients of thermal expansion (CTE) of their constituent layers. Relative to room temperature, as shown in the cross sections of FIG. 2, the IC chip 220 at an elevated temperature of approximately 250° C. shows a slight negative warp, i.e., the IC chip's center is lower than the corners; whereas, the chip carrier 240 shows a positive warp, i.e., the chip carrier's center is higher than its corners. The relatively more compliant chip carrier typically warps to a greater extent than does the IC chip. Warping represents a change in height of sub-areas across the surface area of either the IC chip or the chip carrier at an elevated temperature relative to a reference plane at room temperature.
The extent of warping of the IC chip and the chip carrier is proportional to a radial distance from a centrally located neutral point, i.e., DNP, of each of the IC chip and the chip carrier. Hence, the relative distance between the opposing solders on the IC chip and the chip carrier is greatest at the greatest radial distances from the DNPs, i.e., above the edges and corners of the IC chip. At peak elevated temperatures, the solder bumps or Cu pillars above the edges and corners of the IC chip, and the solder of the opposing FC attaches are physically separated and contact is impossible.
Experiments indicate that warpage above the edges and corners of the IC chip results in gaps of 10 or more microns between the surfaces of the solder bumps or Cu pillars and their corresponding FC attaches in a flip chip package. Such a gap results in a warpage-related “nonwet” problem, where the opposing miscible solders cannot mix.
The mechanical stresses and strains that occur with chip package interactions (CPIs) are complex, depending upon many factors including IC chip design, chip carrier design, process variations in IC chip and chip carrier manufacture, and process variations in bond and assembly. Many CPIs result from stress/strain caused by a mismatch between the coefficients of thermal expansion (CTE) of the IC chip and the chip carrier during the processes of heating the solder of the solder bumps or CU pillars to their melting point and the subsequent cooling of the joined IC chip and chip carrier to an ambient temperature. Differences in contraction during cool-down result in shear forces between the IC chip and the chip carrier. These shear forces are usually propagated as stress/strain through the solder bumps or Cu pillars to an interface region with the IC chip.
One type of chip package interaction (CPI) is a so-called “white bump” because of the white area produced on photographically processed acoustic images during test of the flip chip package. Each white bump corresponds to the location of a material fracture or layer separation in the region below the solder bump or Cu pillar and within the IC chip-level circuitry. Frequently, the white bump resembles a divot formed beneath a solder bump or Cu pillar in the back-end-of-line (BEOL) layers of the IC chip. White bumps typically occur at the IC chip's edges and corners, where shear forces resulting from warpage are greatest. In addition, a white bump is usually located on the compressive peripheral edge of the solder bump or Cu pillar, which is subject to a radially-directed tensile stress during cool-down.
Redistribution layers (RDLs) are widely used in modern IC chip-side technology to re-orient a final BEOL-level wiring pattern for compatibility with different packaging options. Referring to FIG. 3, a standard RDL structure typically makes use of a first continuous polyimide layer 310 between the final BEOL layer 320 of the IC chip and the RDL wiring/pad layer 330, to “cushion” or mitigate mechanical stress. A second continuous polyimide layer 340 is used as a final passivating layer. However, fabrication of an RDL structure with two full-thickness continuous polyimide layers, each of approximately 10 μm thickness, subsequently gives rise to unacceptable levels of IC chip-side warpage from polyimide tensile stresses during flip chip packaging. In a worst case, these polyimide tensile stresses preclude wafer or chip-level processing beyond the polyimide curing process.
It is known that polyimide formed into discrete “island” structures can enable local reduction of CPI stresses without creating the unacceptable warpage of a continuous layer's application.
There remains a need to compensate for the gap produced by warpage and chip package interactions (CPIs), including “white bumps”, in the making of flip chip packages by using a chip-side redistribution layer (RDL) that includes polyimide.